… the three outputs will release (thus going high by external pull up resistor)
Being an IC designer by trade, the idea of using Silego’s GreenPak looked both intimidating and interesting at the same time. It’s interesting to hook up analog blocks on the fly but the learning curve to use GreenPAK designer – whoof. That was my impression at first, or still is? Let’s find out.
Disclaimer: One of efabless’s pursuits is to bring community together to create chips and make effective use of open source hardware. I spend my efforts towards the Chiplicity goal of this company’s vision. So I’m naive when it comes to using Silego’s GreenPAK designer (and their Programmable Mixed Signal Matrix). I thought of experimenting with GreenPAK for system design i.e. to use it as a poor man’s Simulink or alternative to Richard Schrier’s CPP Sim. But I must say, it’s way more than that – you not only get to design your system, you also get to burn it down as a chip that can be soldered on PCB and fire up as your own custom mixed-signal ASIC (figuratively speaking).
It was a typical Saturday afternoon, when I thought I would checkout Silego’s challenge on our platform. I must say, being a die-hard analog guy, the idea of designing power sequence system is always a yuk against spending hours trying to design an OTA from scratch. It took me a while to get convinced to begin this challenge’s system design with the following rough sketch,
*ENR is (EN)able (R)eady – the new enable signal after considering Power-ON-Reset (POR)’s stance on signal given to EN pin.
So if you go to challenge page and look at power sequencer challenge #1 details, you will notice that the target specs require a 60 ms power delay line (x3) with enable strobing functionality (i.e. EN pin). Oh, this is for power up sequence. They also have a target spec for power down sequence, which I must admit was bit overwhelming for someone not quite good with digital logic. Basically the timing diagram should look roughly like this (check the challenge page for the actual timing specification) for OUTx signals (for x = 1, 2 and 3; my notation),
Let’s begin with GreenPAK designer – the reason why I wrote this post – to get over the learning curve as quickly as I can. First, create a new project,
Now add these details:
I added VDD and temperatures ranges from the target specification docx file under Files tab in the Challenge #1 page. Now time to watch a 5 minute video on how to use GreenPAK designer. That’s all I watched for completing this challenge. When was the last time you popped open manual to use iPhone!
Youku link (Chinese)
You should also checkout other videos as challenges progress, but if time is of concern – 5 minutes is all you need. Check other training videos out here. PSA: there is NO undo function. You gotta use Erase Wire or Erase Label since GreenPak is all about reconfiguring connection amongst predefined macro blocks.
Wiring up the entire design with selection of components, the initial design looked like this,
Now, let’s define delay of 60 ms. I would encourage to read pp 59-60 of SLG46110 datasheet. It gives details about the onboard RC oscillator with the ability to prescale clock frequency (seems like APLL with R-divider f/b – a speculation). There are various flavors to get 60 ms delay. I chose this one (with CLK/24 setting),
CLK/24 setting looks like this,
Now the final design configured for delay (without pins) should look like this,
Note that I’ve updated pin properties in accordance with this in the target specification document,