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      What is Caravel Mini and how to use it?

      Caravel Mini is a project template provided by efabless to have 4 projects on the same chip

      Using the Caravel Mini project is an excellent way to prototype your design, especially for small designs that do not require the entire user_project_wrapper. This approach can be cost-effective while still offering significant benefits.

      This template can be shared with other users, and you have the option to keep your project private if desired. Other teams sharing the same chip will not have access to your project's documentation, GDS, or any other files.

      How does Caravel Mini work

      Caravel Mini has 4 user project areas, in the same user project space in Caravel chip, as seen in the image below:

      To switch between projects, there's a mux that selects the projects based on IOs 36 and 37. For this project you only need to worry about your user project design and let efabless do the rest. efabless will take your design and integrate it inside Caravel Mini, and then inside Caravel through our Tapeout process.

      Your project can also be private, other teams on the same chip will not have access to your project's documentation, gds, or any other files.

      Caravel Mini Features

      1. Area of each project is 1300 um x 1600 um
      2. 36 programmable GPIOs
      3. 32 Logic Analyzer probes
      4. 32 bit Wishbone bus connected to the mgmt SoC
      5. 1 digital power domain

      Caravel Mini Limitations

      1. Analog IOs are not supported
      2. Highest metal used in any project is metal 4
      3. Fixed PDN

      Installation

      To install all dependencies and start working on your project, follow these steps:

      1. Visit caravel user mini repo
      2. Press the Use this template button to create your own repository.
      3. Clone the repository: 
        git clone https://github.com/<yourusername>/<your_new_repo_name>.git

        cd <your_new_repo_name>
      4. setup the environment: 
        make setup

        This will download all necessary dependencies.

      Update verilog

      You can update the RTL Verilog file located at verilog/rtl/user_project_wrapper_mini4.v. This file contains an example counter design that you can replace with your own design. You can also include macros within the user project.

      You have the flexibility to include macros as either soft macros, which will be hardened together with the user project, or as hard macros, which can be integrated directly into the user project. Regardless, the user project should be the top-level module that you harden and submit to the platform.

      RTL Verification

      You can use the Cocotb infrastructure to run RTL verification. It is already set up; you just need to add a new test bench. Example test benches can be found under verilog/dv/cocotb.

      To run the simulation, use the following command:

      make cocotb-verify-<name_of_testbench>-rtl

      Hardening Your Design

      To harden your design using OpenLane, ensure that you adjust the configuration file located at openlane/user_project_wrapper_mini4/config.json as needed.

      To start the hardening process, run:

      make <macro_name>

      Remember, the user project should be the top-level module in your design hierarchy for the final hardening and submission. You can include both soft and hard macros within this top-level module.

      To harden the top level user_project_wrapper_mini4 macro run

      make user_project_wrapper_mini4