IP maturity levels give a better understanding where IP blocks stand in the IP development lifecycle. This provides a better understanding of the risk involved in using the IP in your project.
IP blocks in the Efabless Marketplace have seven levels of maturity. They are:
- Defined - The IP Block definition is complete.
- Implemented - The IP Block design is complete.
- Verified - The IP Block design is fully verified and ready for integration.
- Integrated - The IP Block is integrated onto at least one chip.
- Validated - The IP Block functionality is validated on silicon.
- Characterized - The IP Block is fully characterized on silicon.
- Production - At least 10,000 chips have been manufactured containing this IP Block.
These levels are defined as:
- Defined:
The IP block definition is complete. The IP block is fully defined and all functionality, interfaces, pins, AC/DC parameters, views, and test plans are documented. The preliminary floorplan and the list of layout views are included in the documentation for hard IP. Placement guidelines are also available. - Implemented:
The IP block design is complete. For soft IP the RTL is complete and preliminary views are available. The RTL has been fully simulated and the gate count estimated. Lint, CDC, equivalence, power domain crossing, etc have been completed. The IP block can be integrated and used for preliminary chip planning (it will not break flow).
For hard IP the schematic/netlist is complete. The block has been fully simulated and meets all specifications. The block area estimate is complete and floorplan updated if needed. - Verified:
The IP block is verified and ready for integration. For Soft IP the RTL has been synthesized, constraints written, and PNR testing completed. The gate count has been verified and FPGA Validation complete. Lint, CDC, equivalence, power domain crossing, etc. is complete. The IP block is ready for final chip integration.
For hardened IP the RTL has been hardened and simulated. The IP block meets specs. IR drop analysis has been completed and final views generated. LVS/DRC checks are complete with zero errors.
For hard IP the layout is complete, extracted, and all simulations are completed meeting all specifications. The final views are generated. LVS/DRC checks are complete with zero errors. - Integrated:
The IP block has been successfully integrated in at least one chip. For soft IP the full chip synthesis is complete and constraints updated. Scan-insertion is complete if applicable. The IP block has been fully simulated at the full chip level (behavior, GL, scan, DFT, BIST, etc). Any necessary updates to the IP block (integration learning) have been fully vetted at the Verified level. For hardened and hard IP the IP block has been integrated in a chip at least once. The IP block has passed all physical and simulation verifications. Any updates to the block (integration learning) have been fully vetted at the "Verified" level. - Validated:
The IP block has been tested in silicon and is fully functional to all test plans, or updates have been made to the IP block documentation listing any gaps to functionality. - Characterized:
The IP block has been fully characterized on silicon and is 100% functional to test plans. All parameters have been characterized across corners and the IP block fully meets specifications, or agreement has been made to change the specifications to match silicon. If necessary, any updates have been made to the IP block documentation listing any gaps to the IP block specifications. - Production:
The IP block is in high-volume production. At least one chip containing the IP block has passed the "Characterization" step and at least 10,000 chips have shipped containing the IP block.
These maturity levels enable users to fully understand the state of the IP block and understand the risk of using each IP block.