This is a guide on how to use OpenFrame, using a simple timer example
The OpenFrame Project provides an empty harness chip that differs significantly from the Caravel and Caravan designs. Unlike Caravel and Caravan, which include integrated SoCs and additional features, OpenFrame offers only the essential padframe, providing users with a clean slate for their custom designs.Key Characteristics of OpenFrame
- Fully customizable Design:
- No integrated SoC or additional circuitry.
- Only includes the padframe, a power-on-reset circuit, and a digital ROM containing the 32-bit project ID.
- Padframe Compatibility:
- The padframe design and pin placements match those of the Caravel and Caravan chips, ensuring compatibility and ease of transition between designs.
- in types are identical, with power and ground pins positioned similarly and the same power domains available.
- Flexibility:
- Provides full access to all GPIO controls.
- Maximizes the user project area, allowing for greater customization and integration of alternative SoCs or user-specific projects at the same hierarchy level.
- Configurable I/O:
- Pins that previously connected to CPU functions (e.g., flash controller interface, SPI interface, UART) are now repurposed as configurable general-purpose I/O, making it more complicated, but offers more flexibility for various applications.
Features
- 44 configurable GPIOs.
- User area of approximately 15mm².
- Supports digital, analog, or mixed-signal designs.
openframe_timer_example
This example implements a simple timer and connects it to the GPIOs.
Installation and Setup
First, clone the repository:
git clone https://github.com/efabless/openframe_timer_example.gitThen, download all dependencies:
cd openframe_timer_example
make setup
Hardening the Design
In this example, we will harden the timer. You will need to harden your own design similarly.
make user_proj_timerOnce you have hardened your design, integrate it into the OpenFrame wrapper:
make openframe_project_wrapper
Important Notes
- Connecting to Power:
- Ensure your design is connected to power using the power pins on the wrapper.
- Use the
vccd1_connection
andvssd1_connection
macros, which contain the necessary vias and nets for power connections.
- Flattening the Design:
- If you plan to flatten your design within the
openframe_project_wrapper
, do not buffer the analog pins using standard cells.
- If you plan to flatten your design within the
- Running Custom Steps:
- Execute the custom step in OpenLane that copies the power pins from the template DEF. If this step is skipped, the precheck will fail, and your design will not be powered.