How to Integrate Your Design Done by Commercial Tools into user_project_wrapper

This article explains how to integrate designs created with commercial tools into user_project_wrapper, with the top-level integration performed using OpenLane.

Hardening Your Design

Successfully hardening your design requires careful attention to several key aspects, including timing, clock synchronization, power distribution, routing, and layout compatibility. The following sections provide detailed guidance on each of these considerations to ensure a seamless integration process.

Timing

• Ensure you use the user_project_wrapper SDC file, modifying it to fit the format required by your tool.
• Adjust the SDC file to account for the wires connecting your design to the user_project_wrapper pins.
• Verify through logs that the SDC file is read correctly and that delays are properly accounted for.

Clock

• It is recommended to use the Wishbone clock (wb_clk_i) if you are utilizing the Wishbone interface or Logic Analyzers.
• If you prefer using user_clock2, implement a synchronizer to synchronize the two clocks.

Power

• Follow the specific Power Distribution Network (PDN) guidelines for the user_project_wrapper. Power is on metal layers 4 and 5.
• Ensure your design LEF file does not have obstructions over metal layers 4 and 5.
• If you opt for a power ring around your macro, ensure the LEF file does not obstruct the rings on metal layers 4 and 5.
• Avoid signal routing near the power rings to prevent short circuits or DRC errors.

Routing

• Ensure pins are accessible for routing from the wrapper to your macro.
• The LEF file should not have obstructions over the pins in the metal layers where the pins are defined.

Layout

Commercial tools may generate files that are not fully compatible with OpenLane. Ensure compatibility through OpenLane's logs. Common files that might need modification include:

• GDS File: Check that standard cells are defined and not just placeholders. Load the GDS file in KLayout and inspect the cell hierarchy. Placeholder cells are indicated by parentheses around their names.
• LEF File: Adjust obstructions to make the PDN and signal pins available for routing.
• DEF File: Check for and correct any syntax errors, which can be identified in the OpenLane log files.
• GL Netlist: Flatten hierarchical netlists, as OpenLane does not support them.