Development Milestones and Checklist for Digital Design Projects with ChipIgnite

The document outlines a basic development process for your project, including pre-check and tapeout jobsubmission steps found on the Efabless web platform.

ChipIgnite is a platform for designing and submitting chip projects. This document is intended for users new to chip design who are designing and implementing a digital design using the OpenLane open-source EDA design flow.  

The document outlines a basic development process for your project, including pre-check and tapeout job submission steps found on the Efabless web platform. It also incorporates the use of OpenLane for design implementation, RTL simulation, and includes steps for physical verification and post-STA review.

• Project Definition and Block Diagram
  • Milestone: Define the functionality for your project including a pin definition. Develop a high-level block diagram showing the main components of your chip and determine any IP requirements
  • Checklist:

• • • Define the pinout for each of the chip IO used for the design
    • Identify the major functional blocks (e.g., processor, memory, communication interfaces).
    • Define the data flow between these blocks.
    • Create a block diagram for the design
    • Are there any performance requirements?
    • Consider any IP requirements including blocks from the Efabless Marketplace including SRAM, digital or analog blocks.
  • Timing: T minus 8-10 weeks

• Design and Simulate Your RTL Code
  • Milestone: Implement the RTL code representing your chip's functionality.
  • Checklist:

• • • Design the schematic or write RTL code for each block in your architecture.
    • Develop a test bench using your chosen simulation tool to provide stimuli to your RTL code.
    • Write test cases covering various scenarios and edge cases to validate your design's behavior.
    • Analyze the simulation results to ensure the design operates correctly under different conditions.

• • Timing: T minus 6-8 weeks

• Design Implementation using OpenLane 
  • Milestone: Utilize OpenLane for physical design implementation. 
  • Checklist:
    • Update the config.json file for each macro in your design include the user_project_wrapper
    • Run OpenLane for each macro starting with sub-macros and working your way to the top of the design

• • Timing: T minus 5-6 weeks

• Pre-check (Efabless Platform)
  • Milestone: Perform a pre-check on the Efabless platform to ensure your design meets foundry requirements.
  • Checklist:

• • • Upload your design files (including any generated by OpenLane) to the Efabless platform.
    • Run the pre-check tool to identify any errors or violations in your design rules.
    • Address all pre-check errors before proceeding.

• • Timing:  T minus 2-3 weeks
• Tapeout (Efabless Platform)
  • Milestone: Submit a tapeout job on the Efabless platform to perform final assembly, fill generation and physical verification checks.
  • Checklist:

• • • Submit a tapeout job based on a previously successful precheck.  
    • The commit point and design files for the precheck will determine what is used for tapeout.
    • Address any errors with respect to final checks including density issues.

• • Timing:  T minus 1-2 weeks

• Final Submission
  • Milestone: Prepare all necessary documentation and submit your project to ChipIgnite.
  • Checklist:

• • • Ensure you have provide contact and shipping information
    • Also complete the export compliance and terms & conditions
    • Once the above is complete, make sure you submit your design for fabrication

• • Timing: T minus 0 weeks