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      Design Review Checklist

      This document outlines the checklist users should go through before the design review with Efabless technical team.

      Prepare before the design review:

      • Block diagram for the design
        • Add all macros and IPs in your design, and how they should work together
      • Diagram for implementation and integration
        • Show how you are implementing and integrating the design inside the user project wrapper
      • IO mapping for the design
        • Which IOs are being used and their direction
      • For digital designs:
        • RTL code for your design
        • RTL code for the integration with user project wrapper
        • openLane configuration files (if applicable)
        • openLane logs are reports (if applicable)
      • For Analog designs:
        • Design schematic
      • Final GDS layout
      • Local precheck logs and reports
      • Platform precheck and tapeout logs are reports (if applicable)

      Efabless review checklist:

      RTL review (if applicable)

      • Is the example counter removed?
      • Is the top level module instantiated in the user_project_wrapper.v?
      • Is power connected?
      • Are the correct IOs connected, with the correct direction? (based on IO mapping)
      • Are the OEB pins connected, and are they connected to the correct logic?
      • Is the user_defines.v updated, and is it correct?
      • Are IOs[1-4] used? Are there other available IOs to replace them?

      openLane review (if applicable)

      • Is the design hierarchical or flat?
        • If flat, then all the configurations for the example should be reviewed in order to make sure that everything is enabled like CTS, tap insertion, etc…
        • If hierarchical, do they want to have std cells outside their macro? If so, then they need to enable everything like CTS, tap insertion, etc…
        • If hierarchy with no std cells outside the macro, the configuration will stay more or less the same as the example
      • Make sure that all checks are enabled, like DRC, LVS, etc…
      • Check the warnings and errors files, make sure that there are no warnings and errors missed
      • Check timing reports, make sure that there are no violations on the typical nominal, then in the corners
      • Check that there are no checks disabled, and that all reports are clean
      • Check that the analog IOs aren't being buffered by digital standard cells

      OpenFrame review (if applicable)

      • Check that the power pins are correctly placed
      • Check that the design is connected to power, via the power pins

      GDS review  

      • Is the layout DRC clean?
      • Is the layout LVS clean?
      • Are the macros connected correctly, and powered?

      Precheck review

      • Make sure that the run passed with no errors
      • Make sure that all the tests ran